Talk:POWER9

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4 core Sforza series.

"Both POWER9 variants can ship in versions with some cores disabled due to yield reasons, as such a 4-core processor is available from Raptor Computing Systems, but the chip itself is still manufactured with all 24 cores.[6]"

While this sounds highly likely, I see no mention on Raptor's site that their 4-core offering is manufactured in this way. Can anyone offer an additional citation? — Preceding unsigned comment added by 86.186.10.13 (talk) 01:54, 18 November 2017 (UTC)[reply]

I'll be the first to confess that I cant supply source to this, it's "original research". It's been conveyed in private conversation though, but that won't fly as far as wikipedia is concerned. However, there are no sources to corroborate any existence to a POWER9 chip with only four physical cores either. All info from IBM is that there will be two physical core counts, 12× SMT8 and 24× SMT4 cores. In this video (1:57) Rani Borkar (IBM VP OpenPOWER Development) talks about the SO chip (Sforza) "scaling up to 24 cores" while showing graphs for only 24c SO chips, and I take it as disabling due to yield issues, just as they have with all processors since POWER7, or Cell/BE in 2005 really. And not, as a contrast, manufacturing a myriad of chips with different core counts and mounting them in the same package (Talos II will take Sforza chips with more cores when they are available) and socket. NOTHING in what they have said about POWER9 even hints at this scenario, and coming to such a conclusion would be original research too. -- Henriok (talk) 20:11, 18 November 2017 (UTC)[reply]

Here's more info from Raptor regarding their 4- and 8-core Sforza POWER9s. The unused cores are indeed fused off, which creates the interesting benefit of each core get a very large private L3 cache of 10 MB. Usually a SMT4 cores shares the 10 MB L3 with another core. -- Henriok (talk) 19:51, 19 December 2017 (UTC)[reply]

quad

Does POWER9 have quad precision (128 bit) floating point, and POWER8 not have it? Gah4 (talk) 19:58, 3 May 2020 (UTC)[reply]

Yes. Quad floats are a part of PowerISA 3.0 and is not properly implemented in earlier POWER processors, but you can emulate it in software. -- Henriok (talk) 20:12, 4 May 2020 (UTC)[reply]

The reason for the question is that someone (I forget where) mentioned POWER9 for people who need to do it in hardware. So POWER8 has it, but it gives the wrong answers? Gah4 (talk) 21:24, 4 May 2020 (UTC)[reply]

I guess.. I found this article that might shed more light on the matter. -- Henriok (talk) 08:50, 5 May 2020 (UTC)[reply]