User:Riteze

Riteze
Riteze
Born	May 1982
Nationality	India
Alma mater	Centre for Development of Advanced Computing (Master of Technology, Design of 8051 Reduced Instruction Set Computing (RISC) processor, VLSI Design, 2004–2006); Maharishi Markandeshwar Engineering College (Electronics and Instrumentation, Bachelor of Technology, 1999–2003); Kendriya Vidyalaya (All India Senior School Certificate Examination, Secondary School Certificate, 1992–1999);
Occupations	senior lecturer (electronic engineering, Gurgaon, 2006–2006); design engineer (front-end web development, Virage Logic, 2007–2009); lecturer (electronic engineering, 2009–2009); design engineer (front-end web development, Calypto Design Systems, 2009–2011); design engineer (front-end web development, Freescale Semiconductor, 2011–);

Date: 04-11-2024

Notable work

Design of 8051 Reduced Instruction Set Computing (RISC) processor on field-programmable gate array as thesis (2004-2006)